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ICS502
LOCOTM PLL CLOCK MULTIPLIER
Description
The ICS502 LOCOTM is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 MHz. Stored in the chip's ROM is the ability to generate six different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. For applications which require defined input to output skew, use the ICS570B.
Features
* * * * * * * * * * * * * * *
Packaged as 8-pin SOIC or die Available in Pb (lead) free package ICS' lowest cost PLL clock Zero ppm multiplication error Easy to cascade with ICS5xx series Input crystal frequency of 5 - 27 MHz Input clock frequency of 2 - 50 MHz Output clock frequencies up to 190 MHz Low jitter - 50 ps one sigma Compatible with all popular CPUs Duty cycle of 45/55 up to 160 MHz Operating voltages of 3.0 to 5.5 V 25 mA drive capability at TTL levels Industrial temperature version available Advanced, low-power CMOS process
Block Diagram
VDD
S1, S0 X1/ICLK Crystal or Clock input X2
2
PLL Clock Multiplier Circuitry and ROM
CLK
Crystal OScillator
REF
GND
MDS 502 H I n t e gra te d C i r c u i t S y s t e m s
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5 25 Race Stre et, San Jo se, CA 9 5126
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ICS502 LOCOTM PLL Clock Multiplier
Pin Assignment
Clock Decoding Table (MHz)
S1 S0 0 0 1 0 1 0 1 CLK x2 x5 x3 x3.33 x4 x2.5
X1/ I CLK VDD GND REF
1 2 3 4
8 7 6 5
X2 S1 S0 CLK
0 M M 1 1
8 Pi n (150 mi l ) SOI C
Minimum input frequency for all selections is per table on page 3. 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output Input Selection (S1, S0) Output Input Selection (S1, S0) 20 10 0, 0 64 16 1, 0 25 10 1, 1 66.66 20 M, 1 30 10 M, 0 72 24 M, 0 32 16 0, 0 75 15 0, 1 33.33 10 M, 1 80 20 1, 0 37.5 15 1, 1 81 27 M, 0 40 20 0, 0 90 27 M, 1 48 16 M, 0 100 20 0, 1 50 20 1, 1 108 27 1, 0 54 13.5 1, 0 120 24 0, 1 60 20 M, 0 135 27 0, 1
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Name
XI/ICLK VDD GND REF CLK S0 S1 X2
Pin Type
Input Power Power Output Output Input Input Input
Pin Description
Crystal connection or clock input. Connect to +3.3 V or +5 V. Connect to ground. Buffered crystal oscillator output clock. Clock output per table above. Select 0 for output clock. Connect to GND or VDD. Select 1 for output clock. Connect to GND or VDD or float. Crystal connection. Leave unconnected for clock input.
MDS 502 H In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS502 LOCOTM PLL Clock Multiplier
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS502 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and GND. It must be connected close to the ICS502 to minimize lead inductance. No external power supply filtering is required for the ICS502.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -12 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8.
Series Termination Resistor
A 33 terminating resistor can be used next to the CLK pin. The total on-chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be used.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS502. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V -40 to +85C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3
Typ.
-
Max.
+70 +5.5
Units
C
V
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ICS502 LOCOTM PLL Clock Multiplier
DC Electrical Characteristics
VDD=5.0 V 5% , Ambient temperature 0 to +70C, unless stated otherwise
Parameter
Operating Voltage Input High Voltage, ICLK only Input Low Voltage, ICLK only Input High Voltage Input Low Voltage Input High Voltage Input Mid Voltage Input Low Voltage Output High Voltage Output Low Voltage IDD Operating Supply Current, 20 MHz crystal Short Circuit Current On-Chip Pull-up Resistor Input Capacitance, S1, S0, and OE
Symbol
VDD VIH VIL VIH VIL VIH VIM VIL VOH VOL
Conditions
ICLK (pin 1) ICLK (pin 1) OE (pin 7) OE (pin 7) S0, S1 S1 S0, S1 IOH = -25 mA IOL = 25 mA No load, 100 MHz CLK output Pin 7 Pins 4, 6, 7
Min.
3 (VDD/2)+1
Typ.
Max.
5.5 (VDD/2)-1
Units
V V V V V V V
2 0.8 VDD-0.5 VDD/2 0.5 2.4 0.4 20 +70 270 4
V V V mA mA k pF
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ICS502 LOCOTM PLL Clock Multiplier
AC Electrical Characteristics
VDD = 5.0 V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise
Parameter
Input Frequency, crystal input Input Frequency, clock input Output Frequency, VDD = 4.5 to 5.5V Output Frequency, VDD = 3.0 to 3.6V Output Frequency, VDD = 4.5 to 5.5V Output Frequency, VDD = 3.0 to 3.6V Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle PLL Bandwidth Output Enable Time, OE high to output on Output Disable Time, OE low to tri-state Absolute Clock Period Jitter One Sigma Clock Period Jitter
Symbol
FIN FIN FOUT FOUT tOR tOF tOD
Conditions
Min.
5 2
Typ.
Max.
27 50 160 120 190 140
Units
MHz MHz MHz MHz MHz MHz ns ns
-40 to +70C -40 to +85C +25C +25C 0.8 to 2.0 V 2.0 to 8.0V 1.5V, up to 160 MHz
14 14 14 14 1 1 45 10 50 50 49-51
55
% kHz ns ns ps ps
tja tjs
Deviation from mean
+70 25
MDS 502 H In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS502 LOCOTM PLL Clock Multiplier
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Symbol Millimeters Min Max Inches Min Max
Index Area
EH
Pin 1
D
h x 45 0
A A1 B C D E e H h L a
1.35 1.75 1.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 Basic 5.80 6.20 0.25 0.50 0.40 1.27 0 8
0.0532 0.0688 0.0040 0.0098 0.013 0.020 0.0075 0.0098 .1890 .1968 0.1497 0.1574 0.050 Basic 0.2284 0.2440 0.010 0.020 0.016 0.050 0 8
A Q e b c
Ordering Information
Part / Order Number
ICS502M ICS502MT ICS502MI ICS502MIT ICS502MLF ICS502MLFT ICS502MILF ICS502MILFT ICS502-DWF ICS502-DPK
Marking
ICS502M ICS502M ICS502I ICS502I 502MLF 502MLF 502ILF 502ILF -
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Die on uncut, probed wafers Tested die in waffle pack
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C
Parts that are ordered with an "LF" suffix to the part number are the Pb-free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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525 Ra ce Street, San Jose, CA 9512 6
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